Reversing the order of a group of objects in logarithmic time

ABSTRACT

The order of a group of objects is reversed in logarithmic time. The invention may be applied to a wide variety of applications. An exemplary embodiment is included in which the invention may be used to reverse the order of the bits contained in a computer register.

FIELD OF THE INVENTION

[0001] The present invention relates generally to the manipulation ofobjects and, more specifically, to reversing the order of a group ofobjects.

BACKGROUND OF THE INVENTION

[0002] A common problem is that of reversing the order of a group ofobjects. This problem occurs in fields as diverse as the collation ofpages in a document, the sorting of records in a database, thearrangement of dancers in a choreographed performance, and the reversalof bits in a computer storage register. In the latter case, for example,bit reversal is often accomplished by operating on a single bit at atime or by using one or more look up tables. Further, some bit reversalmethods rely on looping, branching, and memory accesses that reducespeed and efficiency. The other applications listed above and manyothers benefit from a rapid, efficient method for reversing the order ofa group of objects, whatever those objects happen to be. It is thusapparent that there is a need in the art for an improved method forreversing the order of a group of objects.

SUMMARY OF THE INVENTION

[0003] A method is provided for reversing the order of a group ofobjects. An apparatus is also provided for implementing the method inthe context of an exemplary embodiment of the invention.

[0004] Other aspects and advantages of the present invention will becomeapparent from the following detailed description, taken in conjunctionwith the accompanying drawings, illustrating by way of example theprinciples of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0005]FIG. 1A is an illustration of a group of objects whose order is tobe reversed.

[0006]FIG. 1B is an illustration of the group of objects shown in FIG.1A after a first partitioning of the objects into sub-groups has beenperformed in accordance with an exemplary embodiment of the invention.

[0007]FIG. 1C is an illustration of the group of objects shown in FIG.1A after the positions of the sub-groups shown in FIG. 1B have beeninterchanged in accordance with an exemplary embodiment of theinvention.

[0008]FIG. 1D is an illustration of the group of objects shown in FIG.1A after a second partitioning of the objects into sub-groups has beenperformed in accordance with an exemplary embodiment of the invention.

[0009]FIG. 1E is an illustration of the group of objects shown in FIG.1A after the positions of adjacent pairs of sub-groups shown in FIG. 1Dhave been interchanged in accordance with an exemplary embodiment of theinvention.

[0010]FIG. 1F is an illustration of the group of objects shown in FIG.1A after a third partitioning of the objects into sub-groups has beenperformed in accordance with an exemplary embodiment of the invention.

[0011]FIG. 1G is an illustration of the group of objects shown in FIG.1A after the positions of adjacent pairs of sub-groups shown in FIG. 1Fhave been interchanged in accordance with an exemplary embodiment of theinvention.

[0012]FIG. 2 is a flowchart and illustration showing how the inventionmay be applied to the reversal of bits in a computer storage register inaccordance with an exemplary embodiment of the invention.

[0013]FIG. 3A is a diagram showing a first portion of the operation ofan exemplary implementation of the method shown in FIG. 2.

[0014]FIG. 3B is a diagram showing a second portion of the operation ofan exemplary implementation of the method shown in FIG. 2.

[0015]FIG. 3C is a diagram showing a final portion of the operation ofan exemplary implementation of the method shown in FIG. 2.

[0016]FIG. 4 is a functional block diagram of a circuit for performingthe processing steps shown in the exemplary implementation of FIG. 3.

[0017]FIG. 5A is an illustration in accordance with another exemplaryembodiment of the invention before a row of pixels has been reversed.

[0018]FIG. 5B is an illustration in accordance with another exemplaryembodiment of the invention shown in FIG. 5A after the row of pixels hasbeen reversed.

DETAILED DESCRIPTION OF THE INVENTION

[0019] The invention has broad applicability to any situation in whichthe order of a group of objects must be reversed. For example, theinvention may be used to reverse the order of pages in a document, toimplement a card trick, to reorder a line of dancers in a choreographedperformance, to reorder records in a database, or to reverse the orderof bits in a computer register. The invention is particularly usefulwhen the number of objects in the group is a positive-integer power oftwo.

[0020] FIGS. 1A-1G show a step-by-step overview of the process ofreversing the order of a group of objects in accordance with anexemplary embodiment of the invention. FIG. 1A shows a group of objects100 numbered from 1 to 8. Eight objects have been included in the figurefor simplicity in explaining the invention. The principles of theinvention generalize to any number of objects that is a positive-integerpower of two. In FIG. 1B, the group of objects 100 has been partitionedinto two sub-groups, 105 and 110, each of which contains an equal numberof objects (in this case, four). FIG. 1C shows the group of objects 100after the positions of subgroups 105 and 110 have been interchanged. InFIG. 1D, the group of objects 100 as reordered in FIG. 1C has beenpartitioned into four sub-groups (115, 120, 125, and 130) of two objectseach. In FIG. 1E, the positions of adjacent pairs of sub-groups in FIG.1D have been interchanged. In FIG. 1F, the group of objects 100 asreordered in FIG. 1E has been partitioned into eight sub-groups (135,140, 145, 150, 155, 160, 165, and 170) of one object each. Finally, inFIG. 1G, the positions of adjacent pairs of sub-groups formed in FIG. 1Fhave been interchanged to compete the reversal of the order of theoriginal group of objects 100 shown in FIG. 1A.

[0021] In the particular exemplary embodiment discussed in connectionwith FIGS. 1A-1G, the partitioning of the group of objects 100 intosub-groups proceeds from coarse to fine. Each partitioning of a group ofobjects into sub-groups and interchanging adjacent pairs of sub-groups,hereinafter referred to as a “partition-and-interchange step,” may beconsidered a “pass” or “stage” in the reversal process. In the exemplaryembodiment of FIGS. 1A-1G, two sub-groups are formed during the firstpass; on the second, four; and on the third and final pass, eight. Inother words, the group of objects is partitioned, on each of threepasses, into a unique set of subgroups containing the same number ofobjects. In general, for 2^(N) objects, the group of objects ispartitioned into log₂(2^(N))=N unique sets of equally sized sub-groups.For the unique set of 2^(j) sub-groups associated with the jth pass(j=1, 2, 3, . . . , N), each sub-group contains 2^((N−j)) objects.However, the order in which the N partition-and-interchange steps areperformed is arbitrary. For example, the sub-groups may instead progressfrom fine to coarse, in which case the unique set of 2^((N−j+1))sub-groups associated with the jth pass (i=1, 2, 3, . . . , N) comprisessub-groups of 2^((j−1)) objects each. Furthermore, there is norequirement that the unique sets of sub-groups contain monotonicallyincreasing or decreasing numbers of sub-groups. In fact, thepartition-and-interchange steps may be performed in any desired order.Stated more formally, it may be easily verified that the order of agroup of 2^(N) objects may be reversed by selecting a set of N integerscomprising all powers of two between 1 and 2^((N−1)), inclusive;partitioning the group of 2^(N) objects into sub-groups, each sub-grouphaving a number of objects equal to a unique one of the set of Nintegers; interchanging the positions of adjacent pairs of sub-groups;and repeating the process for the remaining (N−1) integers in the set.Note that the group of objects operated upon during all passessubsequent to the first pass is the result of the previous pass. In thespecific example shown in FIG. 1A involving a group of eight objects100, N equals 3, and a set of integers comprising 1, 2, and 4 may beselected. The group of objects 100 is partitioned into three unique setsof sub-groups, each sub-group within a given set having a number ofobjects equal to a unique one of these three integers (1, 2, or 4).Thus, the number of objects in each sub-group during the three passescould be any one of, respectively, 1, 2, and 4; 1,4, and 2; 2, 4, and 1;2, 1, and 4; 4, 1, and 2; or 4, 2, and 1 for a total of six possibleorderings. The choice of an ordering depends on the application and theimplementer's preferences. Assuming that each partition-and-interchangestep is performed in one time unit (all interchanges of position takeplace simultaneously during each partition-and-interchange step), agroup of 2^(N) objects may be reversed in a time proportional tolog₂(2^(N))=N, in logarithmic time. That is, letting M=2^(N), theperformance is O(log(M)).

[0022] The embodiment discussed in connection with FIGS. 1A-1G may alsobe interpreted from a recursive point of view, although the performanceof a recursive implementation is sub-optimal (O(M)). In FIG. 1B, thegroup of objects 100 has been subdivided into two sub-groups (105 and110) of equal size, and the positions of the two sub-groups areinterchanged to result in the new ordering shown FIG. 1C. The sameprocedure is next applied recursively to each sub-group 105 and 110,resulting in each sub-group 105 and 110 being further subdivided intotwo sub-groups (115, 120, 125, and 130), as shown in FIG. 1D. Withineach newly subdivided sub-group 105 and 110, the positions of the twonew sub-groups are interchanged (115 with 120 and 125 with 130), asshown in FIG. 1E. The same procedure is again applied recursively tosub-groups 115, 120, 125, and 130, resulting in each sub-group beingfurther subdivided into two sub-groups (135, 140, 145, 150, 155, 160,165, and 170), as shown in FIG. 1F. Within each newly subdividedsub-group 115, 120, 125, and 130, the positions of the two newsub-groups are interchanged (135 with 140, 145 with 150, 155 with 160and 165 with 170), as shown in FIG. 1G. At this point, the process iscarried no further because each sub-group comprises a single object, andthe group of objects 100 is in reverse order. In general, a group of2^(N) objects may be reversed by recursively subdividing the group ofobjects into two sub-groups of equal size and interchanging thepositions of the two sub-groups. Recursion terminates when eachsub-group comprises a single object and adjacent pairs of single-objectsub-groups have been interchanged.

[0023]FIG. 2 is a flowchart and illustration showing how the inventionmay be applied to the reversal of bits in a computer storage register inaccordance with an exemplary embodiment of the invention. The inventionis particularly useful for reversing the order of the bits in a bitpattern using primitive instructions available in most modernmicroprocessors. In FIG. 2, byte 205 represents a bit pattern to bereversed. At 210, byte 205 is partitioned into eight sub-groups of onebit each, and the positions of adjacent pairs of single bits areinterchanged to produce first intermediate result 215. At 220, firstintermediate result 215 is partitioned into four sub-groups of two bitseach, and the positions of adjacent pairs of two-bit sub-groups areinterchanged to produce second intermediate result 225. At 230, secondintermediate result 225 is partitioned into two sub-groups of four bitseach, and the positions of the two four-bit sub-groups are interchangedto produce final result 235. The process is then terminated at 240. Themethod illustrated in FIG. 2 may be applied to anypositive-integer-power-of-two register size. For example, a 32-bit word(25 bits) may be reversed in five partition-and-interchange steps. Asmentioned previously, in reversing the order of a bit pattern comprising2^(N) bits, the order in which the N partition-and-interchange steps areperformed is arbitrary. For example, in FIG. 2, a variation in which twofour-bit sub-groups are interchanged first, followed by the interchangeof adjacent pairs of single-bit sub-groups, followed by the interchangeof adjacent pairs of two-bit sub-groups, is equally valid.

[0024] There are many possible implementations to accomplish theinterchange operation during each pass (partition-and-interchange step)of the method illustrated in FIG. 2. FIGS. 3A-3C show one way in whichthe interchange operation may be implemented: bit shifting and masking,which are readily available operations in most computing devices. Themethod shown in FIGS. 3A-3C is particularly advantageous because theposition interchanges during each partition-and-interchange step occursimultaneously, providing true O(log(M)) performance. In FIG. 3A, byte205 is left shifted by one bit at 306 to produce byte 309, which isbit-wise ANDed with hexadecimal constant 0xAA (binary 10101010) at 312to produce a first intermediate result 315. Either sequentially or inparallel (if instruction-level parallelism is employed) with theforegoing steps, byte 205 is right shifted by one bit at 318 to producebyte 321. At 324, byte 321 is bit-wise ANDed with hexadecimal constant0x55 (binary 01010101) to produce a second intermediate result 327. At330, first intermediate result 315 is bit-wise ORed with secondintermediate result 327 to produce result 333. Continuing to FIG. 3B,result 333 comprises the input for the second pass. Result 333 is leftshifted by two bits at 336 to produce byte 339, which is in turnbit-wise ANDed with hexadecimal constant 0xCC (binary 11001100) at 342to produce a first intermediate result 345. In analogous fashion, result333 is also right shifted by two bits at 348 to produce byte 351, whichis in turn bit-wise ANDed with hexadecimal constant 0x33 (binary00110011) at 354 to produce a second intermediate result 357. At 360,first intermediate result 345 and second intermediate result 357 arebit-wise ORed to produce result 363. Continuing to FIG. 3C, result 363comprises the input for the third and final pass. Result 363 is leftshifted by four bits at 369 to produce byte 372, which is in turnbit-wise ANDed with hexadecimal constant 0XF0 (binary 11110000) at 375to produce a first intermediate result 378. Result 363 is also rightshifted by four bits at 381 to produce byte 384, which is in turnbit-wise ANDed with hexadecimal constant 0x0F (binary 00001111) at 387to produce a second intermediate result 390. At 393, first intermediateresult 378 and second intermediate result 390 are bit-wise ORed toproduce final result 396, which is the original byte 205 in reverseorder. The process terminates at 399.

[0025] The exemplary embodiment discussed in connection with 3A-3C maybe implemented in circuit form. FIG. 4 is a functional block diagram ofa circuit to implement the method shown in FIGS. 3A-3C. Register 405 maystore a bit pattern to be reversed. Shifting logic 410, shown in FIG. 4as being divided into left and right portions for conceptualconvenience, shifts the bits contained in register 405 left or right bya positive-integer-power-of-two number of bits, depending on whichpartition-and-interchange step of the method is being performed. Maskinglogic 415, also shown in the functional diagram of FIG. 4 as beingdivided into left and right portions, bit-wise ANDs the shifted bitpattern with a bit pattern comprising an alternating pattern of logical1's and logical 0's, or vice versa. In general, the left-shifted bitpattern is ANDed with a bit pattern comprising j logical 1's followed byj logical 0's, for a left shift of j bits. Likewise, the right-shiftedbit pattern is ANDed with a bit pattern comprising an alternatingpattern of j logical 0's followed by j logical 1's, for a right shift ofj bits. Combining logic 420 bit-wise ORs the output of masking logic 415to produce a result that may be fed back to register 405. Control logic425 controls the operation of shifting logic 410, masking logic 415, andcombining logic 420. For example, control logic 425 may provide index jto shifting logic 410 and masking logic 415 to cause the correct bitshifting and masking operations to be performed during the jthpartition-and-interchange step of the bit reversal process. Controllogic 425 also coordinates the repetition of the shifting, masking, andcombining operations through multiple partition-and-interchange stepsuntil a final bit-reversed result is obtained. The circuit of FIG. 4 isreadily implemented in available computer hardware. For example,shifting logic 410 may be implemented advantageously using a barrelshifter. Masking logic 415 and combining logic 420 may be implementedusing the arithmetic logic unit within most microprocessors. Sucharithmetic logic units may also contain additional registers for storingintermediate results, and a cache memory or on-chip read-only memory(ROM) may be available for storing bit patterns used frequently inmasking operations. Control logic 425 may be implemented using amicroprocessor or microcontroller executing stored program instructions,or using custom logic (e.g., a programmable logic device).

[0026] The exemplary embodiment shown in FIGS. 3A-3C may also beimplemented as program code residing on a computer-readable storagemedium. For example, the program code may, for the reversal of a bitpattern of length 2^(N), comprise a first code segment configured toshift the bit pattern to the left or to the right by j bits to produce ashifted bit pattern, j being a positive-integer power of two less thanor equal to 2^((N−1)); a second code segment configured to bit-wise ANDthe shifted bit pattern with an alternating pattern of j logical 1'sfollowed by j logical 0's to produce a first intermediate result, whenthe bit pattern is shifted to the left by j bits, and to bit-wise ANDthe shifted bit pattern with an alternating pattern of j logical 0'sfollowed by j logical 1's to produce a second intermediate result, whenthe bit pattern is shifted to the right by j bits; and a third codesegment configured to bit-wise OR the first intermediate result with thesecond intermediate result to produce a combined result. Theimplementation may be extended by including a fourth code segmentconfigured to invoke the first, second, and third code segments for eachof N passes or partition-and-interchange steps (bit shifting, masking,and combining or bit-wise ORing). As explained previously, in all passessubsequent to the first pass, the combined result obtained during theprevious pass becomes the bit pattern to which the bit shifting,masking, and combining (bit-wise ORing) operations are applied.

[0027] Although an exemplary embodiment of the invention has beendescribed for reversing the order of bit patterns, the invention mayjust as easily be applied to reversing the order of a group of largerdata objects such as bytes, words, sectors, pages of memory, or pixels.For example, the invention may be applied to the reversal of the orderof a string of alphanumeric characters, including digits drawn fromnumber systems other than the binary number system. In the field ofgraphics, the need sometimes arises to reverse an image, eitherhorizontally or vertically, to create a mirror image of the original.FIG. 5A is an illustration of a bit-mapped raster 500 on which anarbitrary row of pixels 505 has been identified (shown encircled). InFIG. 5A, the size of the pixels has been exaggerated for simplicity indescribing the invention so that the eight pixels, numbered 1-8,represent an entire row or scan line of bit-mapped raster 500.Bit-mapped raster 500 may be associated with, for example, a computermonitor or other display device. The invention may be used to reversethe order of the row of pixels 505, resulting in the configuration shownin FIG. 5B. This process may be repeated on other lines of bit-mappedraster 500 to reverse the entire displayed image. Those skilled in theart will recognize that the same approach may be used to reverse animage vertically by applying the invention to columns of pixels insteadof rows.

[0028] The foregoing description of the present invention has beenpresented for the purposes of illustration and description. It is notintended to be exhaustive or to limit the invention to the precise formdisclosed, and other modifications and variations may be possible inlight of the above teachings. The embodiments were chosen and describedin order to best explain the principles of the invention and itspractical application to thereby enable others skilled in the art tobest utilize the invention in various embodiments and variousmodifications as are suited to the particular use contemplated. It isintended that the appended claims be construed to include otheralternative embodiments of the invention except insofar as limited bythe prior art.

What is claimed is:
 1. A method for reversing the order of a group ofobjects, the number of objects being a positive-integer power of two,the method comprising: (a) partitioning the group of objects into atleast one unique set of subgroups, each sub-group comprising an equalnumber of objects; and (b) interchanging the positions of adjacent pairsof sub-groups within each unique set of sub-groups.
 2. The method ofclaim 1, wherein the objects comprise numerical digits.
 3. The method ofclaim 2, wherein the numerical digits comprise binary bits.
 4. Themethod of claim 1, wherein the objects comprise alphanumeric characters.5. The method of claim 1, wherein the objects comprise pixels on abit-mapped raster.
 6. A method for reversing the order of a group ofobjects, the number of objects being a positive-integer power of two,the method comprising recursively subdividing the group of objects intotwo sub-groups of equal size and interchanging the positions of the twosub-groups.
 7. The method of claim 6, wherein the objects comprisenumerical digits.
 8. The method of claim 7, wherein the numerical digitscomprise binary bits.
 9. The method of claim 6, wherein the objectscomprise alphanumeric characters.
 10. The method of claim 6, wherein theobjects comprise pixels on a bit-mapped raster.
 11. A method forreversing the order of a group of 2^(N) objects, N being a positiveinteger, the method comprising: (a) selecting a set of N integerscomprising all powers of two between 1 and 2^((N−1)), inclusive; (b)partitioning the group of 2^(N) objects into sub-groups, each subgrouphaving a number of objects equal to a unique one of the set of Nintegers; (c) interchanging the positions of adjacent pairs ofsub-groups to produce a result; and (d) repeating steps (b) and (c) foreach of the remaining (N−1) integers, the group of 2^(N) objects in eachsubsequent application of step (b) comprising the result obtained from aprevious application of steps (b) and (c).
 12. The method of claim 11,wherein the N integers are used in monotonically increasing order duringstep (b).
 13. The method of claim 11, wherein the N integers are used inmonotonically decreasing order during step (b).
 14. The method of claim11, wherein the objects comprise numerical digits.
 15. The method ofclaim 14, wherein the numerical digits comprise binary bits.
 16. Themethod of claim 11, wherein the objects comprise alphanumericcharacters.
 17. The method of claim 11, wherein the objects comprisepixels on a bit-mapped raster.
 18. A method for reversing a group of2^(N) objects in N passes, N being a positive integer, the methodcomprising: (a) partitioning the group of 2^(N) objects into 2^((N−j+1))sub-groups, each sub-group containing 2^((j−1)) objects, j equaling oneduring a first pass and increasing by one on each subsequent pass; (b)interchanging the positions of adjacent pairs of sub-groups to produce aresult; and (c) repeating steps (a) and (b) for each of the remaining(N−1) passes, the group of 2^(N) objects in each subsequent applicationof step (a) comprising the result of a previous application of steps (a)and (b).
 19. The method of claim 18, wherein j equals N during a firstpass and decreases by one on each subsequent pass.
 20. The method ofclaim 18, wherein the 2^(N) objects comprise numerical digits.
 21. Themethod of claim 20, wherein the numerical digits comprise binary bits.22. The method of claim 18, wherein the 2^(N) objects comprisealphanumeric characters.
 23. The method of claim 18, wherein the objectscomprise pixels on a bit-mapped raster.
 24. A method for reversing, in Npasses, the order of bits in a bit pattern comprising 2^(N) bits, Nbeing a positive integer, the method comprising: (a) shifting the bitpattern to the left by j bits to produce a left-shifted bit pattern, jequaling one during a first pass and doubling on each subsequent pass;(b) bit-wise ANDing the left-shifted bit pattern with a first maskcomprising an alternating pattern of j logical 1's followed by j logical0's to produce a first intermediate result; (c) shifting the bit patternto the right by j bits to produce a right-shifted bit pattern; (d)bit-wise ANDing the right-shifted bit pattern with a second maskcomprising an alternating pattern of j logical 0's followed by j logical1's to produce a second intermediate result (e) bit-wise ORing the firstintermediate result with the second intermediate result to produce acombined result; and (f) repeating steps (a)-(e) for each of theremaining (N−1) passes, the bit pattern comprising, in each subsequentapplication of steps (a) and (c), the combined result from a previousapplication of steps (a)-(e).
 25. The method of claim 24, wherein jequals N during a first pass and is halved on each subsequent pass. 26.A circuit for reversing the order of bits in a bit pattern comprising2^(N) bits, N being a positive integer, the circuit comprising: aregister to store the bit pattern; shifting logic configured to shiftthe bit pattern to the left or to the right by j bits to produce ashifted bit pattern, j being a positive-integer power of two less thanor equal to 2^((N−1)). masking logic configured to bit-wise AND theshifted bit pattern with an alternating pattern of j logical 1'sfollowed by j logical 0's to produce a first intermediate result, whenthe bit pattern is shifted to the left by j bits, and to bit-wise ANDthe shifted bit pattern with an alternating pattern of j logical 0'sfollowed by j logical 1's to produce a second intermediate result, whenthe bit pattern is shifted to the right by j bits; and combining logicconfigured to bit-wise OR the first intermediate result with the secondintermediate result to produce a combined result.
 27. The circuit ofclaim 26, further comprising: control logic configured to operate theshifting logic, masking logic, and combining logic for each of a set ofvalues of j ranging from one to 2^((N−1)), the bit pattern comprising,for all values of j subsequent to a first value of j, the combinedresult associated with a previous value of j.
 28. The circuit of claim26, wherein the shifting logic comprises a barrel shifter.
 29. A circuitfor reversing the order of bits in a bit pattern of length 2^(N), Nbeing a positive integer, the circuit comprising: means for storing thebit pattern; means for shifting the bit pattern to the left or to theright by j bits to produce a shifted bit pattern, j being apositive-integer power of two less than or equal to 2^((N−1)). means forbit-wise ANDing the shifted bit pattern with an alternating pattern of jlogical 1's followed by j logical 0's to produce a first intermediateresult, when the bit pattern is shifted to the left by j bits, and forbit-wise ANDing the shifted bit pattern with an alternating pattern of jlogical 0's followed by j logical 1's to produce a second intermediateresult, when the bit pattern is shifted to the right by j bits; andmeans for bit-wise ORing the first intermediate result with the secondintermediate result to produce a combined result.
 30. The circuit ofclaim 29, further comprising: means for activating the means forshifting, means for bit-wise ANDing, and means for bit-wise ORing foreach of a set of values of j ranging from one to 2^((N−1)), the bitpattern comprising, for all values of j subsequent to a first value ofj, the combined result associated with a previous value of j.
 31. Thecircuit of claim 29, wherein the means for shifting comprises a barrelshifter.
 32. A computer-readable storage medium containing program codeto reverse the order of bits in a bit pattern of length 2^(N), N being apositive integer, the computer readable storage medium comprising: afirst code segment configured to shift the bit pattern to the left or tothe right by j bits to produce a shifted bit pattern, j being apositive-integer power of two less than or equal to 2^((N−1)); a secondcode segment configured to bit-wise AND the shifted bit pattern with analternating pattern of j logical 1's followed by j logical 0's toproduce a first intermediate result, when the bit pattern is shifted tothe left by j bits, and to bit-wise AND the shifted bit pattern with analternating pattern of j logical 0's followed by j logical 1's toproduce a second intermediate result, when the bit pattern is shifted tothe right by j bits; and a third code segment configured to bit-wise ORthe first intermediate result with the second intermediate result toproduce a combined result.
 33. The computer-readable storage medium ofclaim 32, further comprising: a fourth code segment configured to invokethe first, second, and third code segments for each of a set of valuesof j ranging from one to 2^((N−1)), inclusive, the bit patterncomprising, for all values of j subsequent to a first value of j, thecombined result associated with a previous value of j.